View MAX4889B_8939076.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the MAX4889B/max4889c high-speed passive switch- es route pci express (pcie) data between two possi- ble destinations in desktop or notebook pcs. the MAX4889B/max4889c are quad double-pole/double- throw (4 x dpdt) switches ideal for switching four half lanes of pcie data between two destinations. the MAX4889B/max4889c feature a single digital control input (sel) to switch signal paths. the max4889c is intended for use in systems (e.g., sas) where both the input and output are capacitively coupled, and provides a 10? (typ) source current and a 60k (typ) internal biasing resistor to gnd at the _out_ terminals. the MAX4889B/max4889c are fully specified to oper- ate from a single +3.3v (typ) power supply. both devices are available in an industry-standard 3.5mm x 9.0mm, 42-pin tqfn package. these devices operate over the -40? to +85? extended temperature range. applications desktop pcs notebook pcs servers video graphics cards?li (scaled link interface) and crossfire features ? single +3.3v power-supply voltage ? support pcie gen i, gen ii, and gen iii data rates ? supports sas i, sas ii, and sas 6.0gbps (max4889c) ? superior return loss better than -10db (typ) at 5.0ghz ? small 3.5mm x 9.0mm, 42-pin tqfn package ? industry-standard pinouts MAX4889B/max4889c 2.5/5.0/8.0gbps pcie passive switches ________________________________________________________________ maxim integrated products 1 ordering information 19-4148; rev 2; 8/10 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. evaluation kit available part temp range pin-package MAX4889B eto+ -40? to +85? 42 tqfn-ep* max4889c eto+ -40? to +85? 42 tqfn-ep* pin configuration top view MAX4889B max4889c tqfn 18 19 20 21 gnd v cc gnd v cc 42 + 41 40 39 gnd v cc gnd v cc 1 2 3 4 5 6 7 8 9 1011121314151617 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 coutb+ coutb- din+ din- doutb+ doutb- cin- cin+ v cc boutb- boutb+ bin- bin+ aoutb- aoutb+ ain- ain+ couta- v cc gnd douta+ douta- gnd couta+ gnd sel v cc bouta- bouta+ v cc gnd aouta- aouta+ gnd *connect exposed pad to ground. *ep pci express is a registered service mark of pci-sig corporation. sli is a registered trademark of nvidia corporation. crossfire is a trademark of ati technologies, inc. typical operating circuit appears at end of data sheet.
MAX4889B/max4889c 2.5/5.0/8.0gbps pcie passive switches 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = +3.3v ?0%, t a = t min to t max, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25?, unless otherwise noted.) (note 3) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages referenced to gnd, unless otherwise noted.) v cc ...........................................................................-0.3v to +4v sel, _in_, _outa_, _outb_ (note 1) .......-0.3v to (v cc + 0.3v) continuous current (ain_ to aouta_/aoutb_, bin_ to bouta_/boutb_, cin_ to couta_/coutb_, din_ to douta_/doutb_) .........................................................?0ma peak current (ain_ to aouta_/aoutb_, bin_ to bouta_/boutb_, cin_ to couta_/coutb_, din_ to douta_/doutb_) (pulsed at 1ms, 10% duty cycle)..............................?0ma continuous current (sel).................................................?0ma peak current (sel) (pulsed at 1ms, 10% duty cycle)..................................?0ma continuous power dissipation (t a = +70?) for multilayer board: 42-pin tqfn (derate 35.7mw/? above +70?) .......2857mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? package junction-to-ambient thermal resistance ( ja ) (note 2) ............................................................28.0?/w package junction-to-case thermal resistance ( jc ) (note 2) ..............................................................2.0?/w lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? parameter symbol conditions min typ max units dc performance analog signal range _in_, _outa_, _outb_ -0.3 v cc - 1.8 v on-resistance r on v cc = +3.0v, i _in_ = 15ma, v _outa_ , v _outb_ = 0v, 1.2v 6.4 8.4 on-resistance match between pairs of same channel r on v cc = +3.0v, i _in_ = 15ma, v _outa_ , v _outb_ = 0v (notes 4, 5) 0.1 0.5 on-resistance match between channels r on v cc = +3.0v, i _in_ = 15ma, v _outa_ , v _outb_ = 0v (notes 4, 5) 0.2 on-resistance flatness r flat (on) v cc = +3.0v, i _in_ = 15ma, v _outa_ , v _outb_ = 0v, 1.2v (notes 5, 6) 0.3 _outa_ or _outb_ off-leakage current i _outa_ (off) , i _outb_ (off) v cc = +3.6v, v _in_ = 0v, 1.2v, v _outa_ or v _outb_ = 1.2v, 0v (MAX4889B) -1 +1 a _in_ on-leakage current i _in_ (on) v cc = +3.6v, v _in_ = 0v, 1.2v, v _outa_ or v _outb_ = v _in_ or unconnected (MAX4889B) -1 +1 a output short-circuit current all other ports are unconnected (max4889c) 515a output open-circuit voltage all other ports are unconnected (max4889c) 0.2 0.6 0.9 v note 1: signals on sel, _in_, _outa_, _outb_ exceeding v cc or gnd are clamped by internal diodes. limit forward-diode current to maximum current rating. note 2: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial .
frequency range (ghz) maximum insertion loss (db) 0C2.5 14 25 f ghz +0.6 2.5C5 6 5 f ghz -1.0 5 or greater 8 5 f ghz -3.0 MAX4889B/max4889c 2.5/5.0/8.0gbps pcie passive switches _______________________________________________________________________________________ 3 note 3: all units are 100% production tested at t a = +85?. limits over the operating temperature range are guaranteed by design and characterization and are not production tested. note 4: r on = r on (max) - r on (min) . note 5: guaranteed by design, not production tested. note 6: flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal range. electrical characteristics (continued) (v cc = +3.3v ?0%, t a = t min to t max, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25?, unless otherwise noted.) (note 3) parameter symbol conditions min typ max units ac performance sel-to-switch turn-on time t on_sel z s = z l = 50 80 ns sel-to-switch turn-off time t off_sel z s = z l = 50 , figure 1 15 ns propagation dela y t pd z s = z l = 50 , figure 2 50 ps output skew between pairs t skew1 z s = z l = 50 , figure 2 50 ps output skew between same pair t skew2 z s = z l = 50 , figure 2 10 ps 0hz < f 2.8ghz -14 2.8ghz < f 5.0ghz -8 differential return loss (note 5) s dd11 f > 5.0ghz -3 db differential insertion loss (note 5) s dd21 see table 1 db 0hz < f 2.5ghz -40 2.5ghz < f 5.0ghz -30 differential crosstalk (note 5) s ddctk f > 5.0ghz -25 db 0hz < f 2.5ghz -15 2.5ghz < f 5.0ghz -12 differential off-isolation (note 5) s dd21_off f > 5.0ghz -12 db control input (sel) input logic high v ih 1.4 v input logic low v il 0.6 v input logic hysteresis v hyst 130 mv power supply power-supply range v cc 3.0 3.6 v v cc supply current i cc v sel = 0v or v cc 1 ma table 1. insertion loss mask
MAX4889B/max4889c 2.5/5.0/8.0gbps pcie passive switches 4 _______________________________________________________________________________________ test circuits/timing diagrams load source v out z l MAX4889B/ max4889c sel z s 10% 90% 50% 50% t on_sel t off_sel v out sel the frequency of the signal should be above the highpass filter corner of the coupling capacitors. figure 1. switching time
MAX4889B/max4889c 2.5/5.0/8.0gbps pcie passive switches test circuits/timing diagrams (continued) load source v outp z l v outn z l MAX4889B/ max4889c sel calibration traces v s+ z s v s- z s v calp z l v caln z l v sc+ z s v sc- z s 50% 50% vcm 50% 50% vcm vcm vcm t pdr t pdf t sk1 t sk2 v outn the frequency of the signals should be approximately 1/20 of the lowest data rate. v outp t pd = max (t pdr , t pdf ) t skew = max (t sk1 , t sk2 ) v outp - v outn v calp - v caln figure 2. propagation delay and output skew _______________________________________________________________________________________ 5
MAX4889B/max4889c 2.5/5.0/8.0gbps pcie passive switches 6 _______________________________________________________________________________________ typical operating characteristics (v cc = +3.3v, t a = +25?, unless otherwise noted.) 4.0 5.5 5.0 4.5 6.5 6.0 7.5 7.0 8.0 0 0.6 1.2 1.8 on-resistance vs. v _in_ MAX4889B/9c toc01 v _in_ (v) r on ( ) v cc = +3.0v v cc = +3.6v v cc = +3.3v 3 2 4 5 6 7 8 9 10 0 0.3 0.6 0.9 1.2 1.5 on-resistance vs. v _in_ MAX4889B/9c toc02 v _in_ (v) r on ( ) t a = +85 c t a = -40 c t a = +25 c 250 350 300 500 450 400 650 600 550 700 -40 10 -15 35 60 85 supply current vs. temperature MAX4889B/9c toc03 temperature ( c) supply current ( a) MAX4889B max4889c v cc = +3.6v v cc = +3.3v v cc = +3.0v v cc = +3.6v v cc = +3.3v v cc = +3.0v 0.9 1.0 1.2 1.1 1.3 1.4 3.0 3.2 3.1 3.3 3.4 3.5 3.6 logic threshold vs. supply voltage MAX4889B/9c toc04 v cc (v) logic threshold (v) v ih v il 0 10 20 60 50 40 30 80 70 90 turn-on/-off time vs. supply voltage MAX4889B/9c toc05 v cc (v) turn-on/-off time (ns) 3.0 3.4 3.5 3.2 3.3 3.1 3.6 t on_sel t off_sel -20 -16 -18 -12 -14 -8 -10 -6 -2 -4 0 0246810 differential insertion loss vs. frequency MAX4889B/9c toc06 frequency (ghz) differential inseriton loss (db) MAX4889B max4889c mask -50 -40 -45 -30 -35 -20 -25 -15 -5 -10 0 0246810 differential off-isolation vs. frequency MAX4889B/9c toc07 frequency (ghz) differential off-isolation (db) -80 -60 -70 -50 -20 -10 -30 -40 0 0246810 differential crosstalk vs. frequency MAX4889B/9c toc08 frequency (ghz) differential crosstalk (db) -40 -30 -35 -25 -10 -5 -15 -20 0 0246810 differential return loss vs. frequency MAX4889B/9c toc09 frequency (ghz) differential return loss (db) MAX4889B max4889c mask
MAX4889B/max4889c 2.5/5.0/8.0gbps pcie passive switches _______________________________________________________________________________________ 7 gnd v cc v cc ain+ ain- din+ din- sel aouta+ aouta- aoutb+ aoutb- bin+ bin- bouta+ bouta- boutb+ boutb- cin+ cin- couta+ couta- coutb+ coutb- douta+ douta- doutb+ doutb- sel 0 (default) 1 _in_ to _outa_ on off _in_ to _outb_ off on max4889c MAX4889B control gnd sel din+ din- douta+ douta- doutb+ doutb- cin+ cin- couta+ couta- coutb+ coutb- bin+ bin- bouta+ bouta- boutb+ boutb- ain+ ain- aouta+ aouta- aoutb+ aoutb- control functional diagram/truth table
MAX4889B/max4889c 2.5/5.0/8.0gbps pcie passive switches 8 _______________________________________________________________________________________ pin description pin MAX4889B/ max4889c name function 1 ain+ analog switch 1. common positive terminal. 2 ain- analog switch 1. common negative terminal. 3 aoutb+ analog switch 1. normally open positive terminal. 4 aoutb- analog switch 1. normally open negative terminal. 5 bin+ analog switch 2. common positive terminal. 6 bin- analog switch 2. common negative terminal. 7 boutb+ analog switch 2. normally open positive terminal. 8 boutb- analog switch 2. normally open negative terminal. 9, 19, 21, 26, 31, 34, 39, 41 v cc p osi ti ve s up p l y v ol tag e inp ut. c onnect v c c to a 3.0v to 3.6v sup p l y vol tag e. byp ass v c c to gn d w i th a 0.1? cer am i c cap aci tor p l aced as cl ose as p ossi b l e to the d evi ce. s ee the boar d layout secti on. 10 cin+ analog switch 3. common positive terminal. 11 cin- analog switch 3. common negative terminal. 12 coutb+ analog switch 3. normally open positive terminal. 13 coutb- analog switch 3. normally open negative terminal. 14 din+ analog switch 4. common positive terminal. 15 din- analog switch 4. common negative terminal. 16 doutb+ analog switch 4. normally open positive terminal. 17 doutb- analog switch 4. normally open negative terminal. 18, 20, 22, 25, 29, 35, 38, 40, 42 gnd ground 23 douta- analog switch 4. normally closed negative terminal. 24 douta+ analog switch 4. normally closed positive terminal. 27 couta- analog switch 3. normally closed negative terminal. 28 couta+ analog switch 3. normally closed positive terminal. 30 sel control signal input. sel has a 70k (typ) pulldown resistor to gnd. 32 bouta - analog switch 2. normally closed negative terminal. 33 bouta+ analog switch 2. normally closed positive terminal. 36 aouta- analog switch 1. normally closed negative terminal. 37 aouta+ analog switch 1. normally closed positive terminal. ep exposed pad. connect ep to gnd.
detailed description the MAX4889B high-speed passive switch routes pci express (pcie) data or other high-speed signals with amplitude of 1.2v p-p differential, and common-mode voltage close to 0v between two possible destinations. the MAX4889B is ideal for routing pcie signals to change system configuration. for example, in a graphics application, four MAX4889B devices create two sets of eight lanes from a single 16-lane bus. the max4889c feature a 10? (typ) source current and a 60k (typ) internal biasing resistor to gnd at the _out_ terminals. the max4889c is ideal for dual capacitively coupled applications such as sas and sata. the MAX4889B/ max4889c feature a single digital control input (sel) to switch signal paths. sel has a 70k (typ) pulldown resistor to gnd. the MAX4889B/max4889c are fully specified to oper- ate from a single 3.0v to 3.6v power supply. digital control input (sel) the MAX4889B/max4889c provide a single digital control input (sel) to select the signal path between the _in_ and _out_ channels. the truth tables for the MAX4889B/max4889c are illustrated in the functional diagram/truth table . sel has a 70k (typ) pulldown resistor to gnd. analog signal levels the MAX4889B/max4889c accept standard pcie signals to a maximum of (v cc - 1.8v). signals on the _in+ chan- nels are routed to either the _outa+ or _outb+ chan- nels. signals on the _in- channels are routed to either the _outa- or _outb- channels. the MAX4889B/max4889c are bidirectional switches, allowing _in_ and _out_ to be used as either inputs or outputs. applications information pcie switching the MAX4889B/max4889c primary applications are aimed at reallocating pcie lanes (see the typical operating circuit: video graphics cards ). for example, in graphics applications, several manufacturers have found that it is possible to improve performance by a fac- tor of nearly two by splitting a single 16-lane pcie bus into two 8-lane buses. two of the more prominent exam- ples are sli (scaled link interface) and crossfire. four MAX4889Bs permit a computer motherboard to operate properly with a single 16-lane graphics card, which can later be upgraded to dual cards. board layout high-speed switches require proper layout and design procedures for optimum performance. keep controlled- impedance pcb traces as short as possible or follow impedance layouts per the pcie specification. ensure that power-supply bypass capacitors are placed as close as possible to the device. multiple bypass capac- itors are recommended. connect all grounds and the exposed pad to large ground planes. MAX4889B/max4889c 2.5/5.0/8.0gbps pcie passive switches _______________________________________________________________________________________ 9
MAX4889B/max4889c 2.5/5.0/8.0gbps pcie passive switches 10 ______________________________________________________________________________________ ain+ ain- bin+ bin- cin+ cin- din+ din- aouta+ aouta- bouta+ bouta- couta+ couta- douta+ douta- aoutb+ aoutb- boutb+ boutb- coutb+ coutb- doutb+ doutb- channel select sel channel select sel ain+ ain- bin+ bin- cin+ cin- din+ din- aouta+ aouta- bouta+ bouta- couta+ couta- douta+ douta- aoutb+ aoutb- boutb+ boutb- coutb+ coutb- doutb+ doutb- pcie graphics connector 1 pcie graphics connector 2 pcie north bridge lane 0 tx lane 1 tx lane 2 tx lane 3 tx lane 0 rx lane 1 rx lane 2 rx lane 3 rx MAX4889B MAX4889B v cc gnd v cc gnd typical operating circuit: video graphics cards
MAX4889B/max4889c 2.5/5.0/8.0gbps pcie passive switches ______________________________________________________________________________________ 11 chip information process: cmos package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package draw- ings may show a different suffix character, but the drawing per- tains to the package regardless of rohs status. package type package code outline no. land pattern no. 42 tqfn t423590m+1 21-0181 90-0079
MAX4889B/max4889c 2.5/5.0/8.0gbps pcie passive switches maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 2 8/10 added 8.0gbps pcie passive switch to the title; added gen iii to the data rates in the features section; changed the return loss in the features section to -10db (typ) at 5.0ghz all

▲Up To Search▲

Price & Availability of MAX4889B

	To Download MAX4889B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .